1. Field of the Invention
This invention relates generally to memory systems and, more particularly, to memory systems with reduced memory latency.
2. Background of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
In today""s fast paced world, computer system reliability and performance has become increasingly important. As system architectures become increasingly more complex and as processor speeds are increased through advances in technology, optimizing system performance becomes more difficult. System performance depends in part on the bandwidth and latency of the system""s memory. Typically, memory latency refers to access time and cycle time. Access time is the time between when a read is requested and when the desired data arrives at the requesting device. The cycle time refers to the amount of time between requests to memory. Accessing memory with the lowest latency and the highest use of memory bandwidth is advantageous in computer systems. The longer it takes to access memory (access time) and complete a request (cycle time), the slower the performance of the computer system. Thus, any reduction in access time and/or cycle time may improve system performance.
The present invention may be directed to one or more of the problems set forth above.